This invention relates to microprogram control and, more specifically, is concerned with microprogram controlled data processing apparatus.
U.S. Pat. No. 3,979,729 describes a data processing apparatus in which each machine-level instruction is divided into a number of phases, such as operand address formation, operand fetch, and execute, and each of these phases is implemented by means of a suitable microprogram sequence. An advantage of dividing the instruction into phases is that, in many cases, the same microprogram sequence can be used for corresponding phases of two or more different instructions; this reduces the number of different microprogram sequences required and hence reduces the overall size of the microprogram. For example, a number of different machine instructions may require the address of the operand to be generated in the same way, e.g. by adding a value to a particular base register, and hence these instructions can all share the same microprogram sequence for the address generation phase.
British patent specification No. 1433076 shows a microprogrammed data processing system in which machine-level instructions (macroinstructions) are executed by sequences of microinstructions, and in which each microinstruction is modified by data derived from the machine-level instruction. In this way, the same sequence of microinstructions can be shared between a number of different machine-level instructions. This also reduces the total number of different microprogram sequences required.
However, in spite of the reductions achieved by these techniques, it is still desirable to achieve even greater reductions in the size of the microprogram. This is particularly important where it is desired to implement a complete processor on a single very-large scale integrated circuit (VLSI) chip. The object of the present invention is therefore to provide a way of reducing the size of a microprogram still further, without loss of flexibility in the system.